The present invention relates generally to semiconductor memory designs, and, more particularly, to a semiconductor memory internal timing design.
Semiconductor memories, such as static random access memory (SRAM) or dynamic random access memory (DRAM), have large number of memory cells arranged in arrays. A particular memory cell inside an array is typically selected by a word-line (WL) and a pair of bit-lines (BLs). The WL is typically connected to one or more control gates of every memory cell in a row. In case the control gates are made of NMOS transistors, all the memory cells are turned on when the WL connected thereto turns to a high voltage, i.e., to be activated. The BL pair is typically connected storage nodes of every memory cell in a column to a sense amplifier. The memory cell at the cross point of the activated WL and the BL pair is the one that is selected.
In a modern high density semiconductor memory, the WL may be very long, especially when the word width becomes very large. The WL has to be formed inevitably by one or more metal layers. Even so, delays caused by long WL's resistance and capacitance pose performance limitations and reliability problems in such high density semiconductor memory. Especially with the advances of process technologies which shrink down metal width and thickness, the WL's resistance becomes very significant in comparison with a drive transistor's channel resistance. For instance, for a WL being connected to 256 cells, when in a 65 nm technology, the WL resistance is about 300 ohm; but when in a nm 45 nm technology, the WL resistance is 1027 ohm. At the same time, for a driver's PMOS transistor with a channel width of 10 um, when in a 65 nm technology, the channel resistance is 259 ohm; but when in a 45 nm technology, the channel resistance is 189 ohm. As a result, the ratio between wire resistance and transistor channel resistance drastically increases when technology advances. The higher ratio increases WL slew time, which reduces effective WL pulse width and degrades read/write margin or even causes malfunctions.
FIG. 1 is a waveform diagram illustrating a word-line effective pulse width being reduced due to long slew time. CLK denotes a clock signal 102. A WL pulse 105 is freshly generated from the CLK signal. WL_RC denotes a delayed WL pulse 108 from the initial WL pulse 105 after a long wire RC delay, i.e., the WL_RC is measured at a far end of the WL away from the WL driver. Apparently, longer slew time reduces the effective WL pulse width after the long delay at WL_RC. Such problem is more acute when a process is in a fast/fast corner, meaning parameters of both NMOS and PMOS transistors are made so that such transistors have higher current and operates faster than normal. Because in the fast/fast corner, the pulse width of the initial WL 105 will be reduced. While the RC delay remains relatively constant or significantly less affected by the process variation, the WL_RC pulse width 108 will be reduced, and may eventual cause functional failure.
As such what is desired is a WL tracking scheme that can maintain a proper pulse width even at a far end of the WL.